The Avery Verification IP memory models portfolio provides a complete range of fast and accurate memory models that work with all industry-standard simulators.
Ensure comprehensive verification and protocol and timing compliance. DDR memory VIP portfolio is a comprehensive memory VIP solution portfolio for DDR5/4, LPDDR5/4, RDIMM/LRDIMM/NVDIMM, DFI-PHY, used by system-on-chip (SoC) and memory controller designers using the external SDRAM and DIMM memory components and DFI-PHY developers.
The DDR VIP implements a complete set of models, protocol checkers, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.
Deliverables
