Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CXL3, CXL3.1
Work more efficiently, develop more complex tests and work on more complex topologies, such as multi-path, multi-link solutions. Get maximum productivity and flexibility for the verification of block level, subsystem and system-on-chip (SoC) designs.
Our comprehensive verification solution features an advanced Universal Verification Methodology (UVM) environment that incorporates constrained random traffic generation, robust packet, link and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging and performance analysis metrics.
Avery compliance test suites (CTS) offer effective core through chip-level tests, including those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.
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