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VICS

Accelerated confidence in co-development and co-verification of RTL hardware and firmware/software layers, associated with VIP Interface Protocols

Category:
Description

Why Avery VICS?

Extend verification IP upwards into firmware and software co-simulation. Accelerate confidence by enabling co-development.

System-level co-simulation includes:

  • Complete system-level simulation of actual Linux host OS/SW and SoC HW RTL and embedded SW/FW
  • Virtual platform co-simulation bridges virtual platform (host, embedded) and SoC RTL designs
  • Support for QEMU and Arm Fast models-based virtual platform solutions
  • Seamless transition from simulation VIP-based verification to full-virtual platforms
  • Leverage existing SV/UVM testbenches and VIPs for debugging capabilities
  • Support for HW-SW co-debug, co-verification